The present invention relates to bitline transistor arrangement for flash memory, and more particularly, to a memory array having a plurality of bitline transistors having varying channel widths.
Non-volatile memory (“NVM”) refers to semiconductor memory which is able to continually store information even when the supply of electricity is removed from the device containing such an NVM memory cell. NVM includes Mask Read-Only Memory (Mask ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM) and Electrically Erasable Programmable Read-Only Memory (EEPROM). One common form of EEPROM is flash memory. Typically, NVM can be programmed with data, read and/or erased, and the programmed data can be stored for a long period of time prior to being erased, even as long as ten years.
“Flash memory” is a special type of electrically erasable programmable read only memory (EEPROM) that is known in the art. A normal EEPROM only allows one location at a time to be erased or written, meaning that flash memory can operate at higher effective speeds when the system uses it to read and write to different locations at the same time. All types of flash memory and EEPROM wear out after a certain number of erase operations, due to wear on the insulating oxide layer around the charge storage mechanism used to store data. Flash memory is non-volatile, which means that it stores information on a silicon chip in a way that does not need power to maintain the information in the chip. In addition, flash memory offers fast read access times and solid-state shock resistance.
Flash memory typically stores information in an array of transistors, commonly referred to as “cells,” each of which traditionally stores one bit of information. Flash memory is based on the Floating-Gate Avalanche-Injection Metal Oxide Semiconductor (FAMOS transistor) which is essentially an n-type Metal Oxide Semiconductor (NMOS) transistor with an additional floating conductor “suspended” by insulating materials between the gate and source/drain terminals.
FIG. 1 is a cross sectional view of a conventional flash memory cell 500. The conventional floating gate flash memory cell 500 includes an n+ type source 504, a p type channel 505, an n+ type drain 512 and a p-type substrate 502. A floating gate 506 is sandwiched between an insulating dielectric layer 510 and thin tunnel oxide layer 514 over the channel 505. The floating gate 506 provides the memory storage element for the flash memory cell 500 and is electrically insulated from other elements of the memory cell 500 by the thin tunnel oxide layer 514 and the insulating dielectric layer 510. Control gate 508 is located on top of the insulating dielectric layer 510 and is positioned over the floating gate 506. The floating gate 506 is electrically isolated from the control gate 508 by the insulating layer 510 such as a layer of silicon dioxide (SiO2). The conventional flash memory cell 500 shown is basically an n-channel transistor with the addition of a floating gate 506. Electrical “access” or coupling to the floating gate 506 takes place only through a capacitor network of surrounding SiO2 layers and source 504, drain 512, channel 505, and control gate 508. Any charge present on the floating gate 506 is retained due to the inherent Si—SiO2 energy barrier height, thereby creating a non-volatile memory.
Typically, the structure of the conventional flash memory cell 500 includes a thin tunneling oxide layer 514 on the order of about 100 angstroms (Å), an abrupt drain junction, a graded source junction, oxide-nitride-oxide (ONO) inter-poly oxide and a short electrical channel length on the order of about 0.3 microns or micrometers (μm). Programming a flash memory cell 500 means that charge (i.e., electrons) is added to the floating gate 506. A high drain to source bias voltage is applied, along with a high control gate voltage Vg. The control gate voltage Vg inverts the channel 505, while the drain bias accelerates electrons toward the drain 512. In the process of crossing the channel 505, some electrons collide with the silicon lattice and become redirected toward the Si—SiO2 interface. With the aid of the field produced by the gate voltage Vg some of the electrons travel across the thin oxide layer 514 and become added to the floating gate 506. After programming is completed the electrons added to the floating gate 506 increase the cell's threshold voltage. Programming is selectively performed on each individual cell 500 in an array of cells 500. Reading a flash memory cell 500 is performed using a sense amplifier (not shown). For cells 500 that have been programmed, the turn-on voltage Vt of cells is increased by the increased charge on the floating gate 500. By applying a control gate voltage Vg and monitoring the drain current, differences between a cell with charge and a cell without charge on the respective floating gates can be determined. A sense amplifier compares cell drain current with that of a reference cell such as a flash memory cell 500 which is programmed to the reference level during a manufacturing test. An erased memory cell 500 has more cell current than the reference cell and therefore is a logical “1” whereas a programmed memory cell 500 draws less current than the reference cell and is a logical “0.” Erasing a flash memory cell 500 means that electrons (charge) are removed from the floating gate 506. Erasing flash memory is performed by applying electrical voltages to many cells at once so that the cells 500 are erased in a “flash.” A typical erase operation in a flash memory cell 500 may be performed by applying a positive voltage to the source 504, a negative or a ground voltage to the control gate 508 and holding substrate 502 of the flash memory cells 500 at ground potential. The drain 512 is allowed to “float.” Under these conditions, a high electric field is present between the floating gate 506 and the source 504. The source junction experiences a gated-diode condition during erase and electrons that manage to tunnel through the first few angstroms of the SiO2 of the tunnel oxide layer 514 are then swept into the source 504. After the erase operation has been completed, electrons have been removed from the floating gate 506 thereby reducing the cell threshold voltage Vt. While programming is selective to each individual flash memory cell 500, an erase operation typically includes many flash memory cells 500 in an array being erased simultaneously.
Programming, reading and erasing flash memory cells 500 in a memory array is accomplished by a combination of bitlines and wordlines. Bitline and wordline transistors control voltage and current flow to particular memory cells 500 via the bitlines and wordlines and allow other bitlines to discharge during program, read and erase operations.
U.S. Pat. No. 6,800,908 B2 (Schuelein), the entire contents of which is incorporated by reference herein, discloses an integrated circuit having a voltage generator that selectively increases the voltage potential on a channel region of a transistor relative to a source region of the transistor. Schuelein recognized that as the gate length of a transistor is reduced, the distance between the current carrying electrodes (e.g., source and drain terminals) may also be proportionately reduced. As noted by Schuelein, as the length of the channel region of a transistor is reduced, the electric field of the drain terminal may have a greater effect upon the flow of current in the channel region and reductions in channel length may make it more difficult to control the flow of current across the channel region between the source and drain terminals and lead to an increase in the amount of source-to-drain leakage.
It is desirable to reduce memory array loading effect and memory cell source-side voltage drop from a source-line contact caused by body resistance in a flash memory. It is desirable to provide a memory array having a plurality of bitline transistors having varying channel widths.